Novel programming scheme for segmented word line MRAM array

ABSTRACT

An MRAM array has a plurality of MRAM devices that are arranged in rows and columns with segmented word lines. A magnetic biasing field is coupled to each of the MRAM devices. The MRAM devices are programmed by providing a bidirectional bit line current to a selected bit line of the plurality of bit lines and a word line current pulse to one word line segment of one row of word line segments by discharging coupled word line segments. The field biasing device may be permanent magnetic layers or write biasing lines in proximity to the fixed magnetic layer of each of the MRAM and has a magnetic orientation equivalent to the magnetic orientation of a word line segment magnetic field generated by the word line current pulse.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to memory cells, array structures ofmemory cells, and methods for programming the memory cells. Moreparticularly, this invention relates to magnetic random access memory(MRAM) cells, array structures of MRAM cells, and methods forprogramming MRAM cells. Even more particularly, this invention relatesto programming arrays of MRAM cells having segmented word lines.

2. Description of Related Art

As shown in FIGS. 1 a and 1 b, a memory array is generally formed ofgroups of MRAM cells 10 in columns and rows. Each MRAM cell 10 has anMTJ device 15 for retaining digital data as an orientation of themagnetic fields within the MTJ device 15. Each MTJ device 10 is formedof two layers of magnetic I5 material 16 and 18 isolated from each otherby a tunnel barrier 17. The free magnetic layer 18 is adjoined to thebit line 25. The bit line 25 conducts the bidirectional cell currentI_(c) 35 such that the magnetic field developed by the bidirectionalcell current I_(c) 35 in the bit line 25 and the row write cell currentI_(R) 40 in the row write line conductor 30 determine the magneticorientation of the free magnetic layer 18. The direction of thebidirectional cell current I_(c) 35 determines the state of digital datawithin the MTJ device 15. The word line 30 conducts a row write cellcurrent I_(R) 40 in one direction. The magnetic orientation of the fixedmagnetic layer 16 is determined during manufacturing of the MTJ device15.

The fixed magnetic layer 16 is adjoined to a conductor 45 that isconnected to the drain of an isolation transistor M_(ISO) 20. The sourceof the isolation transistor M_(ISO) 20 is connected to the groundreference point. The gate of the isolation transistor M_(ISO) 20 isconnected to a read word line RWL

In the write operation of the MRAM cell 10, the direction of conductionof the bidirectional cell current I_(c) 35 determines the magneticorientation of the free magnetic layer 18 and thus the digital datastate retained by the MRAM cell 10. During the write process, the readword line RWL 50 deactivates the isolation transistor M_(ISO) 20 toprevent current conduction.

The read operation is illustrated in FIG. 1 b. The read word line RWL 50is set to a state to activate or turn on the isolation transistorM_(ISO) 20. The cell current I_(c) 55 is passed through the bit line 25,through the MTJ device 15, and the isolation transistor M_(ISO) 20 tothe ground reference point. The magnetic orientation of the freemagnetic layer 18 as compared to the magnetic orientation of the fixedmagnetic layer 16 determine the resistance of the MTJ device 15. FIG. 2shows the schematic diagram of the MRAM cell 10 with the MTJ device 15and the isolation transistor M_(ISO) 20 serially connected. The readword line RWL 50 controls the activation and deactivation of theisolation transistor M_(ISO) 20. The bit line 25 is adjoined to the freemagnetic layer 18 for reading the MRAM cell 10.

An MRAM array 100 of the prior art is illustrated in FIG. 3. The MRAMcells 105 are organized in rows and columns to form the MRAM array 100.Each MRAM memory cell 105 is structured and functions as described inFIGS. 1 a and 1 b. Each column of the MRAM memory cells 105 has a bitline 106 a, 106 b, . . . , 106 n-1, 106 n, 107 a, 107 b, . . . , 107n-1, 107 n placed such that the bit line 106 a, 106 b, . . . , 106 n-1,106 n, 107 a, 107 b, . . . , 107 n-1, 107 n is magnetically coupled tothe free magnetic layer of each of the MRAM memory cells 105. Each bitline 106 a, 106 b, . . . , 106 n-1, 106 n, 107 a, 107 b, . . . , 107n-1, 107 n is connected to a current source to receive the bidirectionalcell current I_(c).

Similarly, each row of the MRAM memory cells 105 has a segmented wordline. As illustrated, a group of the MRAM cells are collected intoseparate blocks 110 a and 110 b. The rows of the MRAM cell block 110 ahave the word line segments 108 a, 108 b, . . . , 108 m-1, 108 m and therows of the MRAM cell block 110 b have the word line segments 109 a, 109b, . . . , 109 m-1, 109 m. The word line segments 109 a, 109 b, . . . ,109 n-1, 109 n are placed such that each of the word line segments 108a, 108 b, . . . , 108 m-1, 108 m and 109 a, 109 b, . . . , 109 m-1, 109m is magnetically coupled to the free magnetic layer of each of the MRAMcells 105 on its associated row of MRAM cells.

One end of all of the word line segments 108 a, 108 b, . . . , 108 m-1,108 m are connected to the source of the Block Select transistor 135 ato select the MRAM cell block 110 a. Each of the opposing ends of theword line segments 108 a, 108 b, . . . , 108 m-1, 108 m is connected toa drain of a Row Write Select transistor 120 a, 120 b, . . . , 120 m-1,120 m. The drain of the Block Select transistor 135 a is connected tothe Word Line Current Source 145. The gate of the Block Selecttransistor 135 a is connected to the Block Select Line 140 a. Thesources of each of the Row Write Select transistors 120 a, 120 b, . . ., 120 m-1, 120 m are connected to the current return line 150. Each ofthe gates of the Row Write Select transistors 120 a, 120 b, . . . , 120m-1, 120 m is connected to a Row Write Select Line 115 a, 115 b, . . . ,115 m-1, 115 m. The Block Select Line 140 a controls the activation anddeactivation of the Block Select transistor 135 a to control the flow ofthe Row Write Current I_(R) from the current source 145 through aselected row segment of the MRAM memory cells 105 and a selected RowWrite Select transistors 120 a, 120 b, . . . , 120 m-1, 120 m to thereference current return line 150. The Row Write Select Lines 115 a, 115b, . . . , 115 m-1, 115 m control the activation and deactivation of theRow Write Select transistors 120 a, 120 b, . . . , 120 m-1, 120 m tosteer the Row Write current from the Word Line Current source 145through the selected word line segment 108 a, 108 b, . . . , 108 m-1,108 m.

One end of all of the word line segments 109 a, 109 b, . . . , 109 m-1,109 m are connected to the source of the Block Select transistor 135 bto select the MRAM cell block 110 b. Each of the opposing ends of theword line segments 109 a, 109 b, . . . , 109 m-1, 109 m is connected toa drain of a Row Write Select transistor 125 a, 125 b, . . . , 125 m-1,125 m. The drain of the Block Select transistor 135 b is connected tothe Word Line Current Source 145. The gate of the Block Selecttransistor 135 b is connected to the Block Select Line 140 b. Thesources of each of the Row Write Select transistors 125 a, 125 b, . . ., 125 m-1, 125 m are connected to the current return line 150. Each ofthe gates of the Row Write Select transistors 125 a, 125 b, . . . , 125m-1, 125 m is connected to a Row Write Select Line 115 a, 115 b, . . . ,115 m-1, 115 m. The Block Select Line 140 b controls the activation anddeactivation of the Block Select transistor 135 b to control the flow ofthe Row Write Current I_(R) from the current source 145 through aselected row segment of the MRAM memory cells 105 and a selected RowWrite Select transistors 125 a, 125 b, . . . , 125 m-1, 125 m to thecurrent return line 150. The Row Write Select Lines 115 a, 115 b, . . ., 115 m-1, 115 m control the activation and deactivation of the RowWrite Select transistors 125 a, 125 b, 125 m-1, 125 m to steer the RowWrite current from the Word Line Current Source 145 through the selectedword line segment 109 a, 109 b, . . . , 109 m-1, 109 m.

Each row of the MRAM memory cells 105 has a Read Word Line 130 a, 130 b,. . . , 130 m-1, 130 m connected to the gate of the isolation transistorof each of the MRAM memory cells 105. The Read Word Lines 130 a, 130 b,. . . , 130 m-1, 130 m control the activation and deactivation of theisolation transistors of each of the MRAM memory cells 105 with theselected row of the MRAM array 100 being activated during a readoperation to conduct the read current from the associated bit line 106a, 106 b, . . . , 106 n-1, 106 n, 107 a, 107 b, . . . , 107 n-1, 107 nthrough the MTJ device of the selected MRAM memory cells 105.

Writing one MRAM cell 105 or all the MRAM cells of a row segment of ablock 110 a or 110 b of the MRAM memory cells 105 is shown in the plotof FIG. 4. The Block Select Line 140 a or 140 b is activated to turn onthe selected Block Select transistor 135 a or 135 b for the chosen MRAMcell block 110 a or 110 b. The Row Write Select Line 115 a, 115 b, . . ., 115 m-1, 115 m for the selected row segment of the MRAM cell block 110a or 110 b is activated to turn on the Row Write Select transistors 120a, 120 b, . . . , 120 m-1, 120 m and 125 a, 125 b, 125 m-1, 125 m tosteer the Row Write current I_(R) through the selected word line segment108 a, 108 b, . . . , 108 m-1, 108 m or 109 a, 109 b, . . . , 109 m-1,109 m at the time τ₁. The bidirectional cell current I_(c) is applied atthe time τ₂ to the selected block of MRAM cells through the appropriatebit lines 106 a, 106 b, . . . , 106 n-1, 106 n, 107 a, 107 b, . . . ,107 n-1, 107 n. At the time τ₃, the Block Select Line 140 a or 140 b isdeactivated to turn off the selected Block Select transistor 135 a or135 b for the chosen MRAM cell block 110 a or 110 b and the programmingof the selected row segment of the selected MRAM cell block 110 a or 110b is completed by the termination of the positive or negativebidirectional cell current +I_(C) or −I_(C) at the time τ₄.

The bidirectional cell current I_(c) is either a positive +I_(C) ornegative −I_(C) current dependent on the state of the digital data to beprogrammed to the selected MRAM cells 105.

“High Speed (10-20 ns) Non-Volatile MRAM with Folded Storage Elements,”Ranmuthu, et al., IEEE Transactions on Magnetics, September 1992, Vol.28, Issue 5, pp. 2359-2361 describes an MRAM chip has been designedusing 250 Ω folded memory cells, two-turn word lines, and a high-speeddifferential sensing scheme.

“Optimizing Write Current and Power Dissipation in MRAMs By Using anAsteroid Curve,” Miyatake, et al., IEEE Transactions on Magnetics, May2004, Vol. 40, Issue 3, pp. 1723-1731 describes the analyticalexpressions of minimum electric current and power dissipation, and bitline and word line currents that produce them, for writing data intomagnetic tunnel junction (MTJ) magneto resistive random access memory(MRAM) cells are derived with the assumption that an asteroid curve canbe applied to all MTJs in a memory cell array. The expressions containword length, that is, the number of bits per word, and parasiticresistances of the write word line and bit line (which are importantdesign parameters of memory cell arrays) and distances between the writecurrents and the free magnetic layer for data storage (which areimportant structural parameters of MTJ cells). They provide quantitativeMRAM design guidelines and help to understand current and powerbehavior.

U.S. Pat. No. 6,490,217 (DeBrosse, et al.) teaches an MRAM memory devicethat has a multiple segmented groups. Each segmented group includes anumber of memory cells operatively coupled to a corresponding segmentedword line. Each segmented word line is disposed in relation to theplurality of corresponding memory cells such that the destabilizingcurrent passing through the segmented word line destabilizes thecorresponding memory cells for writing.

U.S. Pat. No. 6,584,006 (Viehmann) provides a segmented MRAM bit lineand word line architecture. Switch circuits are coupled to and locatedalong the adjacent bit lines resulting in the array being divided intosegments along the adjacent bit lines. The segmenting of the bit linesand word lines shortened the programming current path that results indecreased resistance across the device.

U.S. Pat. No. 6,816,405 (Lu, et al.) describes a segmented word linearchitecture for cross point MRAM arrays. The MRAM array magnetic memorycells is arranged in rows coupled to local word lines for assisting inwriting a logical state of the at least one memory cell. The MRAM arrayfurther has global word lines connected to at least one of the pluralityof local word lines. The global word lines are substantially isolatedfrom the memory cells. Write circuits are operatively coupled to theglobal word lines. The write circuits are configurable as a currentsource and/or a current sink for supplying and/or returning,respectively, at least a portion of a write current for assisting inwriting one or more memory cells. The write circuits are configured toselectively distribute the write current across at least a plurality ofglobal word lines so that stray magnetic field interaction betweenselected memory cells and half-selected and/or unselected memory cellsis reduced.

U.S. Pat. No. 6,870,759 (Tsang) and United States Patent Application2004/0165424 (Tsang) illustrate an MRAM array with segmented magneticword lines. Each of the segment word line is coupled with the globalword line(s) such that each segment is separately selectable. Eachsegment is coupled to a portion of the magnetic storage cells.

United States Patent Application 2004/0190360 (Scheuerlein) describes aword line arrangement having multi-layer word line segments forthree-dimensional memory array. The three-dimensional (3D) passiveelement memory cell array provides short word lines while stillmaintaining a small support circuit area for efficiency. Short, lowresistance word line segments on two or more word line layers areconnected together in parallel to form a given word line without use ofsegment switch devices between the word line segments. A shared verticalconnection preferably connects the word line segments together andconnects to a word line driver circuit disposed generally below thearray near the word line. Each word line driver circuit preferablycouples its word line either to an associated one of a plurality ofselected bias lines or to an unselected bias line associated with thedriver circuit, which selected bias lines are themselves decoded toprovide for an efficient multi-headed word line decoder.

SUMMARY OF THE INVENTION

An object of this invention is to provide an MRAM array where selectedMRAM cells are programmed with a current pulse provided by discharging acapacitance resulting from charge present on connected word linesegments.

Another object of this invention is to provide an MRAM array where abiasing magnetic field is provided by permanent magnetic layers isplaced in proximity to each MRAM cell of the MRAM array to allow smallprogramming currents to be applied to the selected MRAM cells.

Further, another object of this invention is to provide an MRAM arraywhere a biasing magnetic field is provided by a write biasing linesplaced in proximity to each MRAM cell of the MRAM array to allow smallprogramming currents to be applied to the selected MRAM cells.

To accomplish at least one of these objects, an MRAM array has aplurality of MRAM devices arranged in rows and columns. A plurality ofbit lines are placed such that each bit line is associated with onecolumn of the columns of the plurality of MRAM devices and is adjoinedto a free magnetic layer of each MRAM device of the column. A pluralityof word lines is placed such that each word line is associated with onerow of the plurality of MRAM devices. Further each of the word lines isdivided into multiple word line segments. A field biasing device isplaced to have a magnetic coupling to each of the plurality of MRAMdevices to provide a magnetic biasing field to each of the MRAM devices.The magnetic biasing field has a magnetic orientation equivalent to themagnetic orientation of a word line segment magnetic field generated bythe word line current pulse.

An MRAM programming circuit is in communication with each of theplurality of bit lines and each of the multiple word line segments ofthe plurality of word line. The programming circuit provides abidirectional bit line current to a selected bit line of the pluralityof bit lines and a word line current pulse to one word line segment ofone row of word line segments. The bidirectional bit line current isactivated at a first time, the word line current pulse is activated tohave a duration from a second time to a third time, and thebidirectional bit line current is deactivated at a fourth time.

The MRAM programming circuit includes block select transistors connectedto each of the word line segments for charging the word line segments toprovide the necessary charge for the word line current pulse. Aplurality of word line segment transistors are coupled between each ofthe multiple word line segments of the plurality of word lines and aword line current return path. When one of the word line segmenttransistors is turned on the word line current pulse passed through theword line segment transistor to the word line current return path. Theword line current pulse is generated by discharging groupings of theword line segments coupled together to the MRAM programming circuit.

The field biasing device, in one embodiment, includes a plurality ofpermanent magnetic layers, each of the permanent magnetic layers isplaced in proximity to the MRAM devices to provide the magnetic biasingfield. In a second embodiment, the field biasing device is formed of aplurality of write biasing lines. Each write biasing line is in closeproximity to each MRAM device of one row of the MRAM devices,essentially parallel to the word line segments of the word lineassociated with the row of MRAM devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a and 1 b are cross sectional diagrams of an MRAM cell of theprior art.

FIG. 2 is a schematic diagram of an MRAM cell of the prior art.

FIG. 3 is a block diagram of an MRAM array.

FIG. 4 is a plot of the bidirectional cell current and word line segmentrow write current of the prior art.

FIG. 5 is an asteroid chart for programming MRAM cells in an array ofthis invention.

FIG. 6 is a cross sectional diagram of a first embodiment of an MRAMcell of this invention.

FIG. 7 is a cross sectional diagram of a second embodiment of an MRAMcell of this invention.

FIG. 8 is a block diagram of a first embodiment of an MRAM array of thisinvention.

FIG. 9 is a plot of the cell current and word line segment referencecurrent of this invention.

FIG. 10 is a block diagram of a second embodiment of an MRAM array ofthis invention.

FIG. 11 is flow chart of the method for programming MRAM cells of thisinvention.

FIG. 12 is a block diagram of an MRAM array of this invention.

DETAILED DESCRIPTION OF THE INVENTION

As shown in FIG. 3, the word line programming current or row write cellcurrent I_(R) 40 is transferred through the selected word line segment108 a, 108 b, . . . , 108 m-1, 108 m or 109 a, 109 b, . . . , 109 m-1,109 m. Any MTJ devices of the MRAM cells 105 not on the selected wordline segment 108 a, 108 b, . . . , 108 m-1, 108 m or 109 a, 109 b, . . ., 109 m-1, 109 m are not affected by the programming current. Referringto FIG. 5, the asteroid chart illustrates the composite characteristicsof MTJ devices of an MRAM cell array 100. It can be shown that theselected word line segment 108 a, 108 b, . . . , 108 m-1, 108 m or 109a, 109 b, . . . , 109 m-1, 109 m can be biased into the shaded region atpoint a such that the positive and negative bidirectional cell currents+I_(C) and −I_(C) of the appropriate bit lines 106 a, 106 b, . . . , 106n-1, 106 n, 107 a, 107 b, . . . , 107 n-1, 107 n having the selectedMRAM cell 105 have a current greater than the current I_(M) at thepoints b and c. The current I_(M) is the required margin for programmingall the MRAM cells 105 and the current I_(s) is the safety margin toinsure the programming but not having the positive and negativebidirectional cell currents +I_(C) and −I_(C) too large.

The row write programming current I_(R) 240 has a very loose toleranceabove the point a of FIG. 5. The only limitation being the level of thedisturb current that is coupled to adjacent word line segments 109 a,109 b, . . . , 109 m-1, 109 m. In MRAM arrays 100 having segmented wordlines, the physical length of the word line segments 109 a, 109 b, . . ., 109 m-1, 109 m is very short and thus the coupling between the wordline segments 109 a, 109 b, . . . , 109 m-1, 109 m is very small.However, as the array densities have increased with the improvements ofmanufacturing technologies, the common nodes 142 a and 142 b that areconnected through the Block Select transistor 135 a or 135 b to thecurrent source 145 have capacitances that become very large. The chargestored at the common nodes 142 a and 142 b when the current source 145is connected through the Block Select transistor 135 a or 135 b issufficiently large to program a selected row segment of MRAM cellsindependent of the current source. Instead of being a constant current,the current is now determined by the capacitance of the common nodes 142a and 142 b, the size of the Row Write Select transistors 120 a, 120 b,. . . , 120 m-1, 120 m, and the current sink of the reference currentreturn line 150. The MRAM array 100 as applied to this invention employsa current pulse in the programming operation. The common nodes 142 a and142 b are precharged for the programming operation by activation of theBlock Select transistor 135 a or 135 b to allow current from the currentsource 145 to flow to the word line segment 108 a, 108 b, . . . , 108m-1, 108 m or 109 a, 109 b, . . . , 109 m-1, 109 m.

To provide a biasing magnetic field for the MTJ device of the selectedMRAM cells 105, the biasing current as shown at point a may be directlygenerated or provided as permanent magnet layer associated with each MTJdevice. Refer now to FIG. 6 for a discussion of a first embodiment ofthe MRAM cell structure where the biasing magnetic field is generated bya biasing current. As described in FIGS. 1 a and 1 b, the MRAM cell 200has an MTJ device 215 for retaining digital data as an orientation ofthe magnetic fields within the MTJ device 215. Each MTJ device 200 isformed of two layers of magnetic material 216 and 218 isolated from eachother by a tunnel barrier 217. The free magnetic layer 218 is adjoinedto the bit line 225. The bit line 225 conducts the bidirectional cellcurrent I_(c) 235 such that the magnetic field developed by thebidirectional cell current I_(c) 235 in the bit line 225 with the rowwrite cell current I_(R) 240 determines the magnetic orientation of thefree magnetic layer 218. The direction of the bidirectional cell currentI_(c) 235 determines the state of digital data within the MTJ device215. The write word line 230 is magnetically coupled to the freemagnetic layer 218 and conducts a row write cell current I_(R) 240 inone direction. The preferred embodiment of the MRAM cell where thebiasing magnetic field for the MTJ device of the selected MRAM cells 105is provided as permanent magnet layer is shown in FIG. 6. The permanentmagnetic layer 265 generates the biasing magnetic field 270. The biasingmagnetic field is structured to be equivalent to that generated by thebiasing current I_(BIAS) 260 thus allowing the small bidirectional cellcurrent I_(c) 235 and the write pulse current of the row write currentI_(R) 240. The permanent magnetic layer 265 is a permanent magnetmaterial such as permalloy, nickel iron, cobalt iron, and any othermagnetic material capable of generating the permanent magnetic biasingfield 270.

A second embodiment of the MRAM cell where the biasing magnetic fieldfor the MTJ device of the selected MRAM cells 105 is provided aspermanent magnet layer is shown in FIG. 7. The basic structure of theMRAM cell 200 is as described in FIG. 6 except the permanent magneticlayer 265 is replaced with the write biasing line 255. The biasingcurrent I_(BIAS) 260 is conducted through the write biasing line 255 togenerate the biasing magnetic field for the programming of the MTJdevice 215 of the MRAM cell 200.

The fixed magnetic layer 216 is adjoined to a conductor 245 that isconnected to the drain of an isolation transistor M_(ISO) 220. Thesource of the isolation transistor M_(ISO) 220 is connected to theground reference point. The gate of the isolation transistor M_(ISO) 220is connected to a read word line RWL 250. The combination of the writebiasing magnetic field, the magnetic field generated by thebidirectional cell current I_(c) 235, and the row write cell currentI_(R) 240 are combined to determine the magnetic orientation of the freemagnetic layer 218 and thus the digital data state the MTJ cell.

An MRAM array incorporating MRAM cell of FIG. 7 is structurally the sameas that shown in FIG. 3. The MRAM cells 105 as described in FIG. 3 arereplaced with the MRAM cells 200 of FIG. 7. The permanent magneticlayers 265 of FIG. 7 providing the biasing magnetic field to allow theprogramming of the MRAM cells of this invention as described hereinafterin FIG. 9. FIG. 8 illustrates an MRAM array incorporating the firstembodiment of the MRAM cells of this invention. The MRAM array 100 isstructured as the MRAM array of the prior art as illustrated in FIG. 3.The MRAM cells 105 of FIG. 3 are replaced with the MRAM cells 200 ofFIG. 6. The fundamental structure is identical to that of the prior artexcept with the addition of the write bias lines 180 a, 180 b, . . . ,180 m-1, 180 m to each row of the array 100 of MRAM cells. The writebias lines are connected to the bias current I_(BIAS) distributionnetwork 175 that is connected to the current source 145. The currentsource 145 generating the bias current I_(BIAS).

Referring to FIG. 9, the magnetic biasing field DB 300 generated by thebiasing current I_(BIAS) 260 of FIG. 6 or the permanent magnetic layer265 of FIG. 7 provides the biasing offset for the fixed reference writecell current I_(R) 305. To program an MRAM cell, a positive cellprogramming current +I_(C) 320 or a negative cell programming current−I_(C) 325 is applied to the bit line of a selected column associatedwith the selected word line segment at the time τ₁. At the time τ₂, thefixed reference write cell current I_(R) 305 is activated to dischargethe selected word line segment. The word line current pulse 315 has anamplitude and duration that is determined by the capacitance of thecommon nodes of the word line segments, the size of the Row Write Selecttransistors, and the current sink of the reference current return line.The positive cell programming current +I_(C) 320 or the negative cellprogramming current −I_(C) 325 are terminated at the time τ₄. Thisunique operating sequence with the bidirectional positive cellprogramming current +I_(C) 320 or a negative cell programming current−I_(C) 325 being turned on followed with a very high word line currentpulse 315 and completed with terminating the low bidirectional positivecell programming current +I_(C) 320 or a negative cell programmingcurrent −I_(C) 325 assures that the free magnetic layer has apredictable magnetic orientation.

Any residual charge present at the capacitance of the common nodes ofthe word line segments may cause unintended programming or disturbanceof adjacent MRAM cells. To alleviate this problem discharge transistorsare connected to the common nodes to discharge the word line segments.Refer now to FIG. 10 for a discussion of an MRAM array 100 withdischarge transistors 350 a and 350 b. The structure of the MRAM array100 is essentially identical to that of the MRAM array of FIGS. 3 and 8with the addition of the discharge transistors 350 a and 350 b.

The drains of the discharge transistors 350 a and 350 b are connected tothe capacitance of the common nodes 142 a and 142 b. The sources of thedischarge transistors 350 a and 350 b are connected to the groundreference point. Alternately, sources of the discharge transistors 350 aand 350 b may be connected to provide a return current to the currentsource/sink 140. The gates of the discharge transistors 350 a and 350 bare connected to receive a word line segment discharge signal 355. Theword line segment discharge signal 355 is activated to turn on aselected discharge transistor 350 a or 350 b at the completion of theprogramming of a selected MRAM cell. The size and structure of thedischarge transistors 350 a and 350 b are tailored to minimize thecurrent the discharge current from the common nodes 142 a and 142 b toprevent any fields developed by the discharge current from disturbingthe state of the MRAM cells 105.

Refer now to FIG. 11 for a summary of the programming of selected MRAMcells on a word line segment. A magnetic biasing field is provided (Box400) for each MRAM cell. The biasing field may be generated by thepermanent magnetic layer 265 of FIG. 6 or the biasing current I_(BIAS)260 of FIG. 7. An address is decoded (Box 405) for column and row toselect the MRAM cells to be programmed. The selected column bit linesare activated (Box 410) with the positive bit line programming current+I_(C) or a negative bit line programming current −I_(C) at the time τ₁.The Row Write Select transistors are activated (Box 415) to dischargethe common word line segment nodes to generate the word line currentpulse I_(R) at the second time τ₂. The word line current pulse has aduration of from the time τ₂ to the time τ₃ and is deactivated (Box420). The selected column bit lines are deactivated (Box 425) at thetime τ₄. This unique operating sequence assures that the free magneticlayer has a predictable magnetic orientation.

Any residual charge present at the capacitance of the common nodes ofthe word line segments may cause unintended programming or disturbanceof adjacent MRAM cells. To alleviate this problem discharge transistorsare activated (Box 430) to discharge the common nodes of the word linesegments to a ground reference point.

An array of the MRAM memory cells having a biasing magnetic field ofthis invention is shown in FIG. 12. An address 500 is received by theword line decoder 505 and the column or bit line decoder 510 andtranslated to select the desired MRAM cells for programming or reading.The column decoder 510 is connected through the upper and lower writelines 515 a and 515 b and upper and lower read/write lines 520 a and 520b to the MRAM arrays 100 a and 100 b. The word line decoder 505 providesthe necessary control signals for activating the selected rows of theMRAM arrays 100 a and 100 b.

The MRAM arrays 100 a and 100 b are constructed in one embodiment fromthe MRAM cells of FIG. 6 and in the second embodiment of the MRAM cellsof FIG. 7 to provide the magnetic biasing field for each of the MRAMcells of this invention. The word line decoder 505 encompasses thefunction of current source 130 of FIGS. 3 and 8 to provide the word lineprogramming current or fixed reference write cell current and thebiasing current of the first embodiment of the MRAM cell of thisinvention.

The column decoder 510 provides the positive or negative bidirectionalcell current +I_(C) or −I_(C) for programming the state of the digitaldata to the free magnetic layer of the first or second embodiment of theMRAM cell of this invention. The timing of the positive or negativebidirectional cell current +I_(C) or −I_(C) and the word lineprogramming current pulse as described in FIG. 9.

The sense amplifiers 525 are connected through the upper and lowerread/write lines 520 a and 520 b to the MRAM arrays 100 a and 100 b tosense the read current during a read operation. The reading of the MRAMcells of the first and second embodiments of this invention is identicalto that described for FIG. 1 b. The sensed data signals is transferredfrom the sense amplifiers 525 to the data driver 530 which amplifies andconditions the sense data for transfer as the output data 535 toexternal data.

The read/write signals 540 and the clocking signals 545 provide thecontrol signals to the control decoder 550. The control decoder 550generating the necessary and timing and control signals for the readingand writing of the MRAM arrays 100 a and 100 b.

While this invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. An MRAM array comprising: a plurality of MRAM devices arranged inrows and columns; a plurality of bit lines, each bit line associatedwith one column of the columns of the plurality of MRAM devices andadjoined to a free magnetic layer of each MRAM device of said column; aplurality of word lines, each word line associated with one row of theplurality of MRAM devices and comprising multiple word line segments,said word line segments in close proximity to a fixed magnetic layer ofeach MRAM device of a sub-grouping of said one row of MRAM devices; anda field biasing device having a magnetic coupling to each of theplurality of MRAM devices to provide a magnetic biasing field to each ofthe MRAM device.
 2. The MRAM array of claim 1 further comprising: anMRAM programming circuit in communication with each of the plurality ofbit lines and each of the multiple word line segments of the pluralityof word line, said programming circuit providing a bidirectional bitline current to a selected bit line of the plurality of bit lines and aword line current pulse to one word line segment of one row of word linesegments.
 3. The MRAM array of claim 2 wherein the bidirectional bitline current is activated at a first time, said word line current pulseis activated to have a duration from a second time to a third time, andsaid bidirectional bit line current is deactivated at a fourth time. 4.The MRAM array of claim 2 wherein said magnetic biasing field has amagnetic orientation equivalent to the magnetic orientation of a wordline segment magnetic field generated by said word line current pulse.5. The MRAM array of claim 2 further comprising a plurality of word linesegment transistors coupled between each of said multiple word linesegments of said plurality of word lines and a word line current returnpath, such that when one of said word line segment transistors is turnedon said word line current pulse passed through said word line segmenttransistor to said word line current return path.
 6. The MRAM array ofclaim 2 wherein said word line current pulse is generated by discharginggroupings of said word line segments coupled together to said MRAMprogramming circuit.
 7. The MRAM array of claim 6 wherein saidprogramming circuit charges said word line segments for discharging toprovide said word line current pulse.
 8. The MRAM array of claim 7wherein said programming circuit includes block select transistorsconnected to each of said word line segments for charging said word linesegments.
 9. The MRAM array of claim 1 wherein the field biasing devicecomprises a plurality of permanent magnetic layers, each permanentmagnetic layers placed in proximity to said fixed magnetic layer of eachof said MRAM devices to provide said magnetic biasing field.
 10. TheMRAM array of claim 1 wherein the field biasing device comprises aplurality of write biasing lines, each write biasing line in closeproximity to each fixed magnetic layer of each MRAM device of one row ofthe MRAM devices, essentially parallel to the word line segments of saidword line associated with said row of MRAM devices.
 11. A method forprogramming an MRAM array comprising the steps of: providing said MRAMarray, said MRAM array comprising a plurality of MRAM devices arrangedin rows and columns; a plurality of bit lines, each bit line associatedwith one column of the columns of the plurality of MRAM devices andadjoined to a free magnetic layer of each MRAM device of said column; aplurality of word lines, each word line associated with one row of theplurality of MRAM devices and comprising multiple word line segments,said word line segments in close proximity to a fixed magnetic layer ofeach MRAM device of a sub-grouping of said one row of MRAM devices; andproviding a magnetic biasing field to each of the plurality of MRAMdevices.
 12. The method for programming said MRAM array of claim 11further comprising the steps of: providing a bidirectional bit linecurrent to a selected bit line of the plurality of bit lines; andproviding a word line current pulse to one word line segment of one rowof word line segments.
 13. The method for programming said MRAM array ofclaim 12 wherein providing said bidirectional bit line current andproviding a word line current pulse comprises the steps of: activatingsaid bidirectional bit line current at a first time; activating saidword line current pulse to have a duration from a second time to a thirdtime; and deactivating said bidirectional bit line current at a fourthtime.
 14. The method for programming said MRAM array of claim 12 furthercomprising the step of: orienting said magnetic biasing field to amagnetic orientation equivalent to the magnetic orientation of a wordline segment magnetic field generated by said word line current pulse.15. The method for programming said MRAM array of claim 12 whereinproviding a word line current pulse comprises the steps of: providing aplurality of word line segment transistors coupled between each of saidmultiple word line segments of said plurality of word lines and a wordline current return path; and turning on one of said word line segmenttransistors so that said word line current pulse is passed through saidword line segment transistor to said word line current return path. 16.The method for programming said MRAM array of claim 12 wherein providinga word line current pulse comprises the steps of: discharging groupingsof said word line segments coupled together to said MRAM programmingcircuit.
 17. The method for programming said MRAM array of claim 16further comprising the step of charging said word line segments toprovide said word line current pulse.
 18. The method for programmingsaid MRAM array of claim 11 wherein providing said magnetic biasingfield comprises the step of: providing a field biasing device said fieldbiasing device comprising a plurality of permanent magnetic layers, eachpermanent magnetic layers placed in proximity to said fixed magneticlayer of each of said MRAM devices to provide said magnetic biasingfield.
 19. The method for programming said MRAM array of claim 11wherein providing said magnetic biasing field comprises the step of:providing a field biasing device comprising a plurality of write biasinglines, each write biasing line in close proximity to each fixed magneticlayer of each MRAM device of one row of the MRAM devices, essentiallyparallel to the word line segments of said word line associated withsaid row of MRAM devices.
 20. An apparatus for programming an MRAM arraycomprising the steps of: means for providing said MRAM array, said MRAMarray comprising a plurality of MRAM devices arranged in rows andcolumns; a plurality of bit lines, each bit line associated with onecolumn of the columns of the plurality of MRAM devices and adjoined to afree magnetic layer of each MRAM device of said column; a plurality ofword lines, each word line associated with one row of the plurality ofMRAM devices and comprising multiple word line segments, said word linesegments in close proximity to a fixed magnetic layer of each MRAMdevice of a sub-grouping of said one row of MRAM devices; and means forproviding a magnetic biasing field to each of the plurality of MRAMdevices.
 21. The apparatus for programming said MRAM array of claim 20further comprising: means for providing a bidirectional bit line currentto a selected bit line of the plurality of bit lines; and means forproviding a word line current pulse to one word line segment of one rowof word line segments.
 22. The apparatus for programming said MRAM arrayof claim 21 wherein means for providing said bidirectional bit linecurrent and means for providing a word line current pulse comprises:means for activating said bidirectional bit line current at a firsttime; means for activating said word line current pulse to have aduration from a second time to a third time; and means for deactivatingsaid bidirectional bit line current at a fourth time.
 23. The apparatusfor programming said MRAM array of claim 18 further comprising: meansfor orienting said magnetic biasing field to a magnetic orientationequivalent to the magnetic orientation of a word line segment magneticfield generated by said word line current pulse.
 24. The apparatus forprogramming said MRAM array of claim 21 wherein means for providing aword line current pulse comprises: means for providing a plurality ofword line segment transistors coupled between each of said multiple wordline segments of said plurality of word lines and a word line currentreturn path; and means for turning on one of said word line segmenttransistors so that said word line current pulse is passed through saidword line segment transistor to said word line current return path. 25.The apparatus for programming said MRAM array of claim 21 wherein meansfor providing a word line current pulse comprises: means for discharginggroupings of said word line segments coupled together to said MRAMprogramming circuit.
 26. The apparatus for programming said MRAM arrayof claim 25 further comprising means for charging said word linesegments to provide said word line current pulse.
 27. The apparatus forprogramming said MRAM array of claim 20 wherein means for providing saidmagnetic biasing field comprises: means for providing a field biasingdevice said field biasing device comprising a plurality of permanentmagnetic layers, each permanent magnetic layers placed in proximity tosaid fixed magnetic layer of each of said MRAM devices to provide saidmagnetic biasing field.
 28. The apparatus for programming said MRAMarray of claim 20 wherein means for providing said magnetic biasingfield comprises: means for providing a field biasing device comprising aplurality of write biasing lines, each write biasing line in closeproximity to each fixed magnetic layer of each MRAM device of one row ofthe MRAM devices, essentially parallel to the word line segments of saidword line associated with said row of MRAM devices.